sram的例句大全

SRAM FPGA system soft simulation designed to realize bitwise write bitwise Reading.

FPGA系统的sram的软仿真设计,可以实现按位写,按位读.

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Presents a circuit of FIFO involving single port SRAM.

提出了一种基于单端口SRAM的 FIFO电路.

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SRAM provides inexpensive storage for temporary data.

SRAM为临时数据提供廉价存储.

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Single event multiple upset ( SEMU ) experimental results of high-density static random access memory ( SRAM ) are presented.

给出典型大容量静态存储器 ( SRAM ) 的多位翻转实验研究结果.

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SRAM devices of ALTERA PLD technology is widely used special allocation of more expensive devices.

SRAM的器件Altera的可编程逻辑器件技术的广泛使用的特别拨款,更昂贵的设备.

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Problem: density memory beyond SRAM is needed in today's devices.

问题: 现今的设计需要优于SRAM的高密度内存.

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ATD made the asynchronous use of SRAM.

地址探测技术的采用保证SRAM的异步应用.

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QDR SRAM is near its interface socket in the board, and as near as possible.

四倍数据率静态存储器和它的接口电路是在同一块板子上, 并且相互之间的距离很近.

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A practical design of a dual-port SRAM embedded in OLED display driver ICs was presented.

详细描述了一种集成在OLED显示驱动芯片中的双端口SRAM设计.

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The SRAM cell illustrated Kuhn's point as she showed the evolution from 90-nm to 45-nm design.

Kuhn出示的90nm到45nm的SRAM单元设计阐明了这点.

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SRAM configuration data storage modules using such devices.

SRAM的配置数据存储单元使用这种设备.

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Data stored in an SRAM is lost when the system is powered down or reset.

当系统断电或重启时,保存在SRAM中的内容将丢失.

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Technology for design and implementation of a programmable embedded asynchronous SRAM controller is presented.

介绍了一种可编程嵌入式异步SRAM存储控制器的设计与实现方法.

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The implementation of MTI processing based on QDR SRAM and FPGA

利用QDR SRAM和FPGA实现雷达动目标显示的方法

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Total Ionizing Dose Effect for Altera SRAM-Based Field Programmable Gate Array

Altera SRAM型现场可编程门阵列总剂量辐射效应

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The MTI processing is implemented with QDR SRAM as the multicycle data memory on the FPGA signal processor.

本文在FPGA信号处理平台上，用QDR SRAM作为雷达多周期数据存储器件，实现了动目标处理功能。

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This paper introduces a master-slave malti-microcomputer numerical control system, which is used 8-bit single chip 8031, qualified STD bus standard, has the structure of fast communication based on the shared RAM ( SRAM).

采用8位单片微机8031，符合STD总线标准，具有公共存储器（SRAM）快速通讯方式，构成主从式多微机数控系统。

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While the five-stage multi-function cycle search pipeline as the kernel and route table being stored in the external ZBT SRAM, it communicates with the host CPU with standard SRAM interface.

此引擎以五级环行多功能流水线为核心，通过SRAM接口与主机交互，采用ZBT SRAM作为路由表存储器。

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FPGA-Based ZBT SRAM Interface Controller

基于FPGA的ZBT SRAM接口控制器的设计

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Design of a ZBT SRAM Controller for a High Speed Remote Sensing Image Compression System

高速遥感图像压缩系统ZBT SRAM控制器的设计

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