Privilege Management Infrastructure ( PMI ) maps user identity to privilege using attribute certificate.

1、

All kinds of vital grafts have similar problems as what PMG has had.

所有活的移植体,多少都具有与腭黏膜移植体相似的缺点.

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2、

This paper explores the application of PMF in-dynamic satellite navigation signal based on fast code acquisition.

文中研究了部分匹配滤波器在高动态卫导信号快速码捕获中的应用.

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3、

In this mode, the position of the vessel is controlled by a PME.

这种模式有时叫见风使舵, 船舶位置由PME控制.

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4、

To date , there has been little reported on PMD monitoring in mixed system.

至今, 只有少数的研究报告关于监测偏振合并调制系统中的偏振色散.

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5、

The concept and description method on PMD and techniques for PMD measurement and compensation are introduced.

介绍了偏振模色散的概念、述方法以及测试和补偿技术.

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6、

Polarization mode dispersion ( PMD ) has a serious obstacle in the development of high-speed optical fiber communication .

偏振模色散 ( PMD ) 已成为高速光纤通信系统发展的严重障碍.

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7、

Automatic measuring system for polarization mode dispersion ( PMD ) was introduced based on improved Poincar é sphere method.

阐述了邦加球法测量偏振模色散 ( PMD ) 的原理,介绍了基于改进的邦加球法开发的PMD测量系统和测量实验.

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8、

If you have received emails from us? plz and surelythe mail address.

汉译英,请问有收到我们邮件么?

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9、

If there is any change, give me a ring plz!

如果有任何变化请立刻通知我.

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10、

I have done the harder work, plz be fair to me , Ok?

我努力了, 请公平点儿吧.

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11、

PLX 9054 is a general PCI controller, it has the property of high performance and friendly interface.

PLX9054是通用的PCI控制器, 具有性能高,接口方便灵活的特点.

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12、

The secondary structures had a little change after PLP removed.

米胚GAD脱辅基后蛋白质的二级结构的变化是部分β-折叠结构转变为了回转结构.

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13、

Therefore , the research of low noise PLL design a very hot topicand of value.

如何减小锁相环路的噪声(时域中称为抖动)是设计者们研究的热门方向.

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14、

A fast locking phase-locked loops ( PLL ) with a dual-slope phase frequency detector circuit is presented.

文中提出了一种用于高速锁相环的双斜鉴频鉴相器的结构设计.

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15、

PLL is used for generating carry synchronization signal.

采用平方环实现载波同步信号的提取.

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16、

PLL frequency synthesizer based on fractional frequency division and ∑-� � technique is introduced.

本文介绍了采用 ∑- △调制技术的小数分频PLL频率合成器.

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17、

Working knowledge of clock synchronization using phase-lock loop ( PLL ).

理解用锁相环 ( PLL ) 实现时钟同步.

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18、

The power consumption due to PLL itself is exclude.

电源损耗由于PLL自身而被排除.

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19、

Outputs serial data transferred from the PLL to the controller.

从PLL输出串行信号到控制器.

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20、

Results: After acute high-altitude, PT, TT, APTT, DD increased and FIB, Plg, plasmin inhibitor decreased ( P < 0.05 ).

结果: 进入高原后, PT 、 TT 、 APTT 、 DD比在平原时增高,FIB 、 Plg 、纤溶酶抑制物降低 ( P<0.05 ).

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