Besides, the technology that we are introducing is second-or-rate technology in those developed countries.

We designed a one-time-copy data path mechanism, making HDSP protocol data packets transferred from network card to hard disk requires only 1 CPU memory copy, without any context switch. 3.

作者设计了一种一次拷贝数据通路机制，使得HDSP协议的数据报文，从磁盘到网卡的传输过程只需要1次CPU内存拷贝，不需要上下文切换。

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The Realization of Embedded CPU Memory Management Unit

嵌入式CPU存储器管理的实现

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This paper firstly introduces hot research field about crosstalk noise such as model building, computing technique, prevention and fix method, then takes the emphasis on the flow implementing signal integrity of Godson-2 CPU memory module.

本文首先阐述了串扰研究领域的热点问题，如模型建立、估算技术、避免与修复方法等，然后将重点放在0.13μm工艺下龙芯2号处理器访存模块的信号完整性实现流程。

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System statistics, including CPU, memory, and disk space

系统统计数据，包括CPU、内存和磁盘空间

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In the kernel mode, create multi-threaded programs, which were concurrently implemented to complete multi-core CPU memory mapping and data synchronization. 4.

在内核态下创建多线程程序，并发执行完成对多CPU核的内存映射及数据同步。

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Besides the physical disk, pay close attention to" Wait"( in the CPU section up top), which also helps determine if the system is I/ O bound.

除了物理磁盘之外，请仔细观察“Wait”（在CPU部分的上部），它也可以帮助确定系统是不是I/O绑定的。

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Design and Realization of Fault-Tolerant Dual CPU Architecture for Centralized Fuel Measuring System

集中式燃油测量系统的双机容错设计与实现

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Research on a Dedicated CPU Architecture for Java IC Card

一种JavaIC卡专用CPU结构研究

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At the minimum, a platform is a combination of a CPU architecture and an operating system.

一个平台至少应该是一种CPU架构和一种操作系统的组合。

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The CPU architecture ( s) to generate machine code for.

产生适合于CPU体系结构的机器码。

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The performance overhead can be ignored due to parallel execution units in the CPU architecture.

与一些软件方法相比，提出的方法充分利用执行单元的并行性，从而极大地减少了对性能的影响。

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The other IRQL levels have meanings that sometimes depend on the parti-cular CPU architecture.

其他的IRQL等级意味着:有时候依赖于专门的CPU体系结构.

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Design Verification via Simulation: Techniques and Their Application in a General-purposed CPU Chip

通用CPU设计中的模拟验证技术及应用

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A Functional Verification Scheme for a DSP& CPU Chip Based on PC and Data Acquisition System

基于PC与数据采集系统的DSP&CPU芯片功能验证方案

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Design and Implementation of a CPU Chip Hardware Test and Debug Platform

一种CPU芯片硬件验证调试平台的设计与实现

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Importing the different virtual CPU chip, can imitate different type experiment on the same virtual platform;

通过引入不同的虚拟CPU芯片，可在同一虚拟平台上实现不同类型的微型机硬件虚拟实验。

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Intelligent Fan Control Device Based on High-speed 16-bit CPU Chip Switchgear

基于高速16位CPU芯片的开关柜风扇智能化控制装置

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Experiments show that this new approach requires less CPU time than the previous method.

实验结果表明，该方法在计算时间上明显优于原来的计算方法。

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In Java technology, threads are usually preemptive, but not necessarily Time-sliced ( the process of giving each thread an equal amount of CPU time).

在java技术中，线程通常是抢占式的而不需要时间片分配进程（分配给每个线程相等的cpu时间的进程）。

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Amount of CPU time in milliseconds used by the event.

事件所使用的以毫秒为单位cpu时间总计。

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